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  • Jason Nieh - Contact Information
    Dept of Computer Science Columbia University Home Research Teaching Publications Facebook Contact Info CONTACT INFORMATION Directions Professor Jason Nieh Columbia University Dept of Computer Science 518 CS Building 1214 Amsterdam Ave MC0401 New York NY 10027 7003 212 939 7160

    Original URL path: http://www.cs.columbia.edu/~nieh/contact.shtml (2016-02-17)
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  • Operating Systems I
    will be dropped in calculating your grade Each assignment will have both non programming and programming problems The programming problems will involve kernel level programming in the Linux operating system 20 Midterm The midterm is one class period closed book calculator permitted The midterm will cover all material discussed in the course up to the week before the exam 30 Final The final exam is scheduled at the normal final exam time for this class period The final is closed book calculator permitted The final is cumulative and will cover all material discussed in the course 0 No extra credit work HOMEWORK POLICY All work is due by the date and time specified in the respective assignment there are no extensions It is much better to submit partially complete homework on time and get partial credit for your work than to submit late homework for no credit Homeworks submitted after the respective deadlines when they are due are considered late Late homeworks will not be accepted unless there is a valid medical or family condition with appropriate documentation submitted to the instructor Submissions should be made electronically using Git a distributed version control system You should use Git for version control of all your code for this class and we will monitor code check ins to see how your work is progressing and who is doing the work Each submission will be time stamped Proper submission is your responsibility we strongly urge you to make sure you understand the submission process and submit early We also urge you to check out your submissions and test them to make sure the submissions are complete You can always submit again up until the deadline so we strongly urge you to submit well before the deadline and then submit again if you have a more updated assignment to submit later GRADING POLICY If you disagree with any homework grade submit your grievance via email to the w4118 staff mailing list documenting the merits of your case The grader responsible will respond likewise via email If you are still dissatisfied you may appeal in like manner to the instructor who will only examine the email record of the dispute and will respond in email If you disagree with any exam grade submit your exam and grievance in writing not email to the grader responsible documenting the merits of your case The grader will respond likewise in writing If you are still dissatisfied you may appeal in like manner to the instructor who will only examine the written record of the dispute and will respond in email For a grade dispute to be considered the written grievance must be submitted in writing within two weeks of when the respective assignment or exam is returned PROGRAMMING POLICY For your convenience all programming can be developed on any Linux machine However only those programs which compile using the gcc compiler in the VM you are given to work with will be graded Furthermore it is critically important

    Original URL path: http://www.cs.columbia.edu/~nieh/teaching/w4118/ (2016-02-17)
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  • Virtual Machines
    and emulate binary translation shadow page tables and device emulation New hardware features introduced by Intel and AMD to assist virtualization will also be covered The second half of the course will survey the classic papers and other recent developments in virtualization In addition to the course instructors we will have guest lecturers who in many cases will cover seminal virtualization papers which they have authored The course provides a unique opportunity to learn from industry leaders in the field This course can be used to satisfy MS track elective requirements for software systems network systems and computer security tracks Because this is a new course it may not be listed yet in the MS degree track requirements INSTRUCTIONAL STAFF Instructor Scott Devine co founder VMware devine vmware com office hours T2 30 4 30PM CSB 464 Instructor Prof Jason Nieh 212 939 7160 office hours M3 5PM CSB 518 COURSE MATERIALS Required Text Virtual Machines Versatile Platforms for Systems and Processes Jim Smith and Ravi Nair Morgan Kaufmann Publishers San Francisco CA 2005 available from Amazon com and Columbia University Bookstore Computing Requirements 50 CS account fee required COURSE GRADE 20 Homework Assignment There will be one homework assignment that involves a small programming mini project assigned to everyone in the class The project will involve systems programming 60 Team Project The project is an opportunity for you to take an active part in exploring the subject area as appropriate for an advanced course You can choose any project you want so long as it has something to do with virtualization The project should be chosen so that it clearly extends your knowledge and understanding of some area of virtualization Projects are to be done in teams of your own choosing Projects can focus on new applications of virtualization

    Original URL path: http://www.cs.columbia.edu/~nieh/teaching/e6998_s08/ (2016-02-17)
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  • embedded systems ultra low energy digital systems low power and robust global communication computer aided design and fault tolerance Dr Nowick is an IEEE Fellow 2009 He received an Alfred P Sloan Research Fellowship 1995 one of 10 awardees that year in all areas of computer science an NSF CAREER Award 1995 and an NSF Research Initiation Award RIA 1993 He received several Best Paper Awards IEEE International Conference on Computer Design both in 1991 and 2012 and the IEEE Async Symposium 2000 He is co founder of the IEEE Async Symposia series and served as its Program Committee Co Chair and General Co Chair He was also Program Chair of the IEEE ACM International Workshop on Logic and Synthesis He has served as a sub committee track chair for several leading design and CAD program committees ACM IEEE Design Automation Conference DAC logic high level synthesis FPGA s ACM IEEE Design Automation and Test in Europe DATE Conference logic technology dependent synthesis and IEEE International Conference in Computer Design ICCD tools and methodologies He is currently an associate editor of IEEE Design Test Magazine IEEE Transactions on VLSI Systems and ACM Journal on Emerging Technologies in Computer Systems and was former associate editor of IEEE Transactions on Computer Aided Design He was also a guest co editor of the Proceedings of the IEEE vol 87 2 Feb 1999 He has been a member of many leading program committees including DAC ICCAD DATE NOCS Async VLSI Design ICCD and IWLS Prof Nowick s recent research has been funded by several NSF awards including for continuous time DSP s 2010 and low latency asynchronous interconnection networks 2012 2008 among others In 2000 he received two medium scale NSF ITR awards for asynchronous research He was brought onto the DARPA CLASS project

    Original URL path: http://www.cs.columbia.edu/~nowick/short-cv.html (2016-02-17)
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  • is on design methodologies and CAD tools for synthesis and optimization of asynchronous and mixed timing i e GALS digital systems His current projects include scalable networks on chip NoC s for shared memory parallel processors and embedded systems ultra low energy digital systems fault tolerance and low power and robust global communication Dr Nowick is an IEEE Fellow and recipient of an Alfred P Sloan Research Fellowship and NSF CAREER and RIA Awards and a senior member of the ACM He received Best Paper Awards at the IEEE International Conference on Computer Design 1991 2012 and the IEEE Async Symposium 2000 He co founded the IEEE Async Symposia series in 1994 and was its Program Committee Co Chair and General Co Chair He was Program Chair of the IEEE ACM International Workshop on Logic and Synthesis IWLS and program track subcommittee chair at DAC DATE and ICCD conferences He is currently an associate editor of IEEE Design Test magazine ACM Journal on Emerging Technologies in Computer Systems JETC and IEEE Transactions on VLSI Systems TVLSI and a former associate editor of IEEE Transactions on CAD TCAD He was selection committee chair of the ACM SIGDA Outstanding Dissertation in EDA

    Original URL path: http://www.cs.columbia.edu/~nowick/journal-style-cv.html (2016-02-17)
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  • ARM And Philips' Handshake Solutions Collaborate To Develop Clockless Processor
    officer Handshake Solutions Applying Handshake Technology to the industry leading ARM architecture will result in a new type of ultra low power processor enabling new classes of application ARM has always been the low power leader in embedded microprocessors said Mike Inglis executive vice president Marketing ARM Our partnership with Handshake Solutions will enable new ultra low power applications in the smart card consumer electronics and automotive markets while preserving the easy integration common to all ARM processors This new ARM processor is compliant with the ARMv5TE architecture and optimized for use in both synchronous and asynchronous system on chip designs permitting easy integration by semiconductor makers The key benefits of the processor include low Electro Magnetic emission reducing the probability of interfering with sensitive circuitry and low peak currents reducing system power requirements Because asynchronous processors consume zero dynamic power when there is no activity they can significantly extend battery life ARM has long recognised the potential of asynchronous design and has supported the Amulet project led by Professor Steve Furber at Manchester University Availability and Tool Support The new ARM processor will be available as a licensable core from ARM in Q1 2005 It will be supported by Handshake Solutions advanced design tools and methodology that enables customers to design a complete or partially asynchronous chip More information on Handshake Solutions can be found at www handshakesolutions com About Royal Philips Electronics Royal Philips Electronics of the Netherlands NYSE PHG AEX PHI is one of the world s biggest electronics companies and Europe s largest with sales of EUR 29 billion in 2003 With activities in the three interlocking domains of healthcare lifestyle and technology and 166 800 employees in more than 60 countries it has market leadership positions in medical diagnostic imaging and patient monitoring color television

    Original URL path: http://www.cs.columbia.edu/~nowick/6936.html (2016-02-17)
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  • Symposium gathers computing greats to decide whether to go clockless
    clock distribution gets larger and larger as the number of transistors gets larger Another way must be found instead of lockstep throughout billions of transistors I expect that the symposium will assess the early macromodular work in the much broader and more difficult context of today s clockless system developments said Clark a Washington University faculty member from 1964 72 and since then a full time consultant The taming of unplanned events in enormous state transition spaces still remains the key challenge in clockless system design Chip designers today are developing chips with diverse clocked domains breaking tasks up into multiple domains Clockless takes that concept a step farther Consider the traffic light example again Imagine sensors for traffic lights that change the colors according to local conditions enabling freedom from the central clock A clocked system must wait until the tardiest signal in the whole bunch makes its transition a clockless system allows for signals to switch without unnecessary waiting for others Clockless computing provides numerous advantages It facilitates easier power supply design reduces noise that a clocked system creates and allows parts of a system to become idle reducing power requirements Theoretically it can lead to faster systems and we re on the threshold of being able to realize that theoretical goal Cox said There is great interest in clockless computing from both industry and the Department of Defense perspectives said Robert Reuss program manager with the Defense Advanced Research Projects Agency The appeals are lower operating power faster performance and reduced electromagnetic interference on the chips A challenge is the complexity of designing very large chips that are approaching one billion transistors Clockless logic has the potential to impact these issues From the Department of Defense perspective we are all the more interested because we do not have the resources to devote to a thorough and long chip design cycle So the DOD is interested in how clockless logic might help us in regards to economy of scale In 1962 future Washington University computer science engineers Clark and the late Charles Molnar and others in MIT s Lincoln Laboratory Group designed the Laboratory Instrument Computer LINC With its digital logic and stored programs the LINC has been recognized by the IEEE Computer Society as the world s first interactive personal computer In 1964 Cox founded the Biomedical Computer Laboratory at the Washington University School of Medicine The same year a team of engineers headed by Clark and Molnar formed the Computer Systems Laboratory at Washington University Together Biomedical Computer Laboratory and Computer Systems Laboratory engineers brought about profound changes in the nature of laboratory and clinical computing worldwide Computing pioneer Ivan Sutherland vice president and fellow of Sun Microsystems will provide the keynote talk on asynchronous computing research at Sun Labs This research has potential for near and medium term integration into Sun products He described the macromodular project at Washington University as the design of an entirely asynchronous set of modules from which one could assemble

    Original URL path: http://www.cs.columbia.edu/~nowick/wash-u-publicity-3-04.html (2016-02-17)
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  • Designers Look To Take Computer Chips Off The Clock
    chips carrying information barely make it between ticks of the 1 GHz chips When 2 GHz chips start to come out in a couple of years however there will be a problem The clock s traditional role will begin to break down The believers in clockless chips known as asynchronous or self timed circuits say it is inevitable clockless chips will eventually replace conventional ones Most of the big firms like IBM Intel and Sun Microsystems have devoted portions of their research and development to asynchronous chips Universities have started teaching students about the clockless concept and there are a number of small startups devoted to the concept Weak Links Asynchronous chips use power only when there is a reason when there is a computing task at hand The transistors on an asynchronous chip can exchange data independently as opposed to conventional chips which must wait for every component to do its job before a task can be completed A conventional chip can run no faster than its slowest component Asynchronous chips can run at the average speed of all components The advantages are numerous Not only are they faster the efficiency of their electrical systems are much higher which means longer battery life In addition they can perform encryption better because they give off no regularly timed signals that hackers can identify and exploit Also asynchronous chips emit very low levels of electromagnetic noise which means they are far less likely to interfere with other devices one of the biggest problems for today s mobile chips Prototypes Exist With their potential to revolutionize the chip industry the logical question is why haven t these chips become more widely adopted Intel Sun Microsystems and IBM all have prototypes that are two to three times faster than their conventional counterparts yet the test chips never made it out of the lab Philips Electronics has an asynchronous chip powered pager that runs almost twice as long as others on the market Few other companies use machines powered exclusively by asynchronous chips though there are some companies that have incorporated asynchronous concepts the Pentium 4 Intel released this year for example Will Catch on Slowly The answer lies in the nature of the semiconductor industry itself Over the course of 20 years the chip industry has invested billions in streamlining testing developing and manufacturing With no mass market to exploit companies have no financial incentives to develop the tools needed to manufacture clockless chips It would take much longer and be more expensive to get the chips to market and few profit driven companies will go to the expense Also it has also proven difficult for companies to find asynchronous designers since the concept is contrary to what most schools have taught for decades Still analysts expect the new chips to catch on slowly especially in the mobile market until conventional chips can no longer do the job Talkback Click here to add your comment about this story Re Designers Look To Take

    Original URL path: http://www.cs.columbia.edu/async/misc/newsfactor_sep_18_2001.htm (2016-02-17)
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