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  • Computing Pioneer Challenges the Clock
    with inventing the field of interactive computer graphics forerunner of contemporary capabilities like computer aided design and virtual reality In 1963 his Ph D thesis described a light pen used to create engineering drawings directly on the cathode ray tube of a computer display Four years later he developed the head mounted display that led directly to the idea of three dimensional virtual reality visors and helmets Then in 1968 he was a co founder of Evans Sutherland which became the world s premier computer graphics company selling graphics systems used by engineers and flight simulators used for training pilots It still makes graphical systems and Mr Sutherland is on the board He joined Sun Microsystems a decade ago when it formed a corporate research laboratory He came with the intention of finding new ways to speed up computing and built a small team with the goal of pioneering a set of technologies to make asynchronous logic a viable option for computer designers This is a fundamental point he said The clock paradigm is running out of steam The tiny community of asynchronous logic proponents is made up of small academic and corporate research teams like Mr Sutherland s and several small start up companies They say that today s conventional chip design process will soon reach its practical limits as processors achieve greater and greater speeds Among other drawbacks the current approach often leaves designers grappling with timing glitches that are maddeningly difficult to debug You solve a problem at one point in a chip and it creates problems in other places that are almost impossible to find said Wesley Clark a computer designer and industry pioneer who has consulted with Mr Sutherland s team at Sun Microsystems Laboratories It adds acre engineer years to the design problem he said referring to the need of chip companies to add another acre of engineers to solve a problem Some researchers have been intrigued by the possibilities of the asynchronous approach to computing since the 1950 s and 60 s when the concept was pioneered by John von Neumann at the Institute for Advanced Study in Princeton N J and by David Muller at the University of Illinois But it has been a largely quixotic quest and today there are only a handful of examples of asynchronous designs that work For example Royal Philips Electronics has built a pager using asynchronous electronics taking advantage of the fact that the circuits produce far less radio interference than do clock driven circuits This makes it possible to operate a radio receiver that is directly next to the electronic circuit greatly increasing the unit s operating efficiency Philips has also actively pursued research into asynchronous logic Two small start ups Asynchronous Digital Design in Pasadena Calif and Theseus Logic in Orlando Fla are developing asynchronous chips for low end consumer markets and high performance computing systems Additionally some longtime computer designers are beginning to use asynchronous logic to solve thorny problems Chuck Seitz an

    Original URL path: http://www.cs.columbia.edu/async/misc/nyt-3-5-2001-sutherland.html (2016-02-17)
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  • Economist.com
    between programs looks a lot less slick Switching involves storing the processor state for the outgoing program that is the configuration of the functional units that do the actual calculations restoring the processor state for the incoming program and then resuming operation This is rather like a chef preparing say eight recipes at once by working on each for say three minutes at a time and then switching recipes Every time he switches he has to forget the old recipe re read the new one and move all of the ingredients on and off his chopping board SMT works by giving the chef a larger chopping board and allowing him to interleave steps from all eight recipes while still ensuring that the peas end up in the pea soup An SMT chip keeps track of several programs or threads at once Doing so requires extra hardware to store the processor state for each thread and when instructions are added to the queue they must be labelled as coming from a particular thread That way when an instruction is sent to one of the various number crunching units on the chip it knows which thread s state to update with the result Engineers at Compaq an American computer maker have estimated that only about 10 more circuitry is needed to enable a conventional chip design to support four threads at once in this way But the improvements in performance can be spectacular because when one of the threads is held up waiting for data to arrive the others can keep running Database and web servers generally create a separate thread for each user request so the ability to run several threads simultaneously is a particular advantage for them Simulations run by Dr Eggers s team have found that an eight thread SMT chip could run database software three times faster than a conventional chip and web server software four times faster And those figures says Dr Eggers are for unmodified software Tweaking the programs to support SMT explicitly could she suggests speed things up even more Stop the clocks Where SMT offers chip designers a big performance gain for a relatively small design change asynchronous logic involves a far more dramatic rethink As its name suggests it does away with the cardinal rule of chip design that everything marches to the beat of an oscillating crystal clock For a 1 GH z chip this clock ticks one billion times a second and all of the chip s processing units co ordinate their actions with these ticks to ensure that they remain in step Asynchronous or clockless designs in contrast allow different bits of a chip to work at different speeds sending data to and from each other as and when appropriate The idea of asynchronous logic goes back to the dawn of digital computers Some of the earliest machines built in the 1950s were based on clockless designs But the synchronous approach predominated largely because it is easier to design chips

    Original URL path: http://www.cs.columbia.edu/async/misc/economist/Economist_com.htm (2016-02-17)
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  • cells A key theme of the course is handling large complex designs entire subsystems or combinational blocks with 1000 s or tens of thousands of gates with very efficient and powerful automated techniques You will be learning and using a variety of heuristic and exact optimization techniques including dynamic programming iterative improvement hill climbing unate and binate covering greedy algorithms and physics based modelling e g force directed scheduling When you have completed the course you will have a good handle on modern research aspects of digital CAD i e the underlying optimization algorithms used to automatically design systems as well as gain some practical hands on experience in using existing CAD packages The course will include assignments that involve programming as well as use of CAD tools You should have at least a solid basic background in programming for this course though you do not need to be a highly fluent programmer If you have questions about your background feel free to contact me by email nowick cs columbia edu or set up an appointment NOTE This is not primarily a project lab course while you will use real CAD tools the focus will be on the optimization algorithms and digital design techniques behind them Also you do not need to be an experienced digital designer to take this course you should simply have a basic background in digital logic SYLLABUS Introduction to modern digital CAD synthesis and optimization techniques Topics include modern system level design and optimization high level synthesis Register transfer level RTL modeling optimal scheduling area vs latency oriented approaches list based and force directed scheduling FDS techniques optimal resource sharing of registers and function units lifetime analysis def use chains sequential logic optimization retiming Optimizing system level area and clock cycle time by local repositioning

    Original URL path: http://www.cs.columbia.edu/~nowick/csee6861-advertisement-11-7-15.txt (2016-02-17)
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  • Recent examples include a trigonometric hardware accelerator floating point add multiply unit on chip network router with error handling DETAILED TOPICS Introduction to modern system level design Register transfer level RTL algorithmic state machine models ASMs datapath control allocation and interconnection System level performance optimization resource sharing scheduling inner loop optimization parallel vs serial organization area delay power tradeoffs Introduction to VHDL an industry standard hardware description language Hands on modelling and simulation of digital systems using Altera CAD tools Structural dataflow and behavioral models Specifying combinational and sequential blocks Synthesis oriented coding styles Large scale digital system case studies Designing and optimizing a custom floating point unit counting and pattern detection units the Philips NXP I2C commercial serial bus interface fault tolerant on chip router nodes encryption decryption units Designing and optimizing digital controllers Mealy and Moore finite state machines FSM s design optimal state encoding and state partitioning Iterative circuits Advanced high performance adders Conditional sum carry skip carry select carry lookahead parallel prefix tree adders Kogge Stone Brent Kung Higher radix arithmetic Power area latency tradeoffs Combinational array multipliers Using carry save addition for optimization Modern low power design techniques Clock gating for controller optimization pre computation logic for pipelined sequential systems low power bus encoding techniques Introduction to fault tolerance and error detection correction Hamming and parity codes 2 dimensional i e product codes cyclic redundancy codes CRC for Ethernet etc Recent work on mitigating soft transient errors due to cosmic rays Introduction to testability and design for test DfT Fault models built in self test BIST techniques scan structures test pattern generation Asynchronous i e clockless digital circuits Controller design high speed pipelines Hazard free logic synthesis Metastability and synchronizers Miscellaneous topics Introduction to FPGA s Xilinx internals and micro architecture Pseudo random number generators

    Original URL path: http://www.cs.columbia.edu/~nowick/csee4823-broadcast-announcement-7-11-15.txt (2016-02-17)
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  • Dana Pe'er Lab
    The page has moved If you browser doesn t redirect you please click here here

    Original URL path: http://www.cs.columbia.edu/~dpeer/ (2016-02-17)
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  • Research Brief | Itsik Pe'er
    methods in human genetics How is it best to measure describe and quantify differences between individual DNA sequences How does sequence variation affect biological processes How can we use it to understand and influence human disease All these questions pose complex analytical challenges with direct impact on medical research Courses CBMF W 4761 Spring 2013 COMS W1005 Fall 2010 Who s new mg2880 itsik2 Vladimir Vacic Anat Kreimer Arthi Ramachandran

    Original URL path: http://www.cs.columbia.edu/~itsik/ (2016-02-17)
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  • Research Page for Kenneth Ross
    Repeats and Somatic Mutation Recent Past Projects Database Parallelism on Multicore Machines The Columbia Fast Query Project Rapid Updates and Snapshot Based Queries Using Multicore Processors Computational Tools for Modeling Visualizing and Analyzing Historic and Archaeological Sites Multiscale Analysis of

    Original URL path: http://www.cs.columbia.edu/~kar/researchprojects.html (2016-02-17)
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  • Home :: Database Research Group :: Columbia University
    Research Group We are interested in high performance database architectures web scale information extraction social media data analysis visualization tools and database theory We are affiliated with the Department of Computer Science and the Data Science Institute News September 2015

    Original URL path: http://www.cs.columbia.edu/database/ (2016-02-17)
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